On 4/4/06, Paul Mullen <[EMAIL PROTECTED]> wrote:
> As I understand it you basically pair 2 x 24bit DSPs to give yourself a 48bit
> fixed point DSP.
>
> The benefits are explained here.
> http://www.jamminpower.com/PDF/48-bit%20Audio.htm
>
> I know it would be more expensive but considering that the ear is very
> sensitive to "pumping" of audio I think it would be worth it if you were
> going to be doing filter on the card and selling it as a pro-audio card.
I've been looking at DAC designs on Wikipedia. It seems that some
high-precision designs use pulse-width or pulse-density modulation and
a low-pass filter to remove the noise from the pulsing. For
precisions higher than 16 bits, it becomes prohibitive to do anything
else. The other major alternative is to use a decoder; you convert
from N bits binary to 2**N bits one-hot and use a resistor array to
analog. Imagine doing with 32 bits. I don't think we could fit the
four billion resistors onto the card. :)
I've been playing with pulse-width modulation (actually, I'd do pulse
density, but what I care about are the achievable ratios).
PWM and PDM encoders are appreciated for their high linearity and low
glitchiness. PDM's are particularly good because for most ratios, the
noise is WAY beyond the bandwidth of your low-pass filter.
My first thought was to take your sample period (5 microseconds for
200KHz sample rate) and divide it by your sample precision (2**32),
but that comes to an absurd frequency (8.5*10**14Hz). The first thing
I realized was that you don't need to use the whole pulse period. For
a pulse period of N cycles, your period can be any M <= N, and your
high can be any H <= M. That is, you can get all of these ratios:
for (M=1; M<=N; M++)
for (H=0; H<=M; H++)
effective_signal_level = H/M;
This doesn't cover everything, and the first thing I noticed was that
the biggest gaps are between 0 and the next higher level and between
1.0 and the next lower level. So, let's go with this:
min = 1/N
max = (N-1)/N
for (M=1; M<=N; M++)
for (H=0; H<=M; H++)
effective_signal_level = (H/M-min)/(max-min);
I ran some experiments and found that, for instance, with 12 bits of
precision in the period (that is, the 5us period is further divided by
4096), and using this ratio approach, you can hit 97% of the signal
levels (+/- 25%) of a 19-bit precision DAC. Unfortunately, this
requires an 800MHz clock.
There are a few solutions to the problem of the 800MHz clock. One is
a hybrid design where we use multiple digital signals and resistors to
weight them. The other is to make use of the differential signalling
abilities that these FPGAs have. LVDS and "Rocket I/O" signals can
run at much faster rates. Instead of clocking one bit at a time, the
logic in the FPGA takes a set of bits that are clocked at N times the
clock rate; this is easy for us to compute.
Another problem left unsolved here is how to encode which ratios apply
to each of the dynamic levels. For 32-bit precision, we don't want to
encode a table of pulse high and low periods that has 4 billion
entries in it.
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