Hamish wrote:
> On Wednesday 21 June 2006 02:15, you wrote:
>   
>> always @(posedge clock) begin
>>     if (drawing_line) begin
>>         ... next step in drawing line ...
>>         if (... last pixel ...) begin
>>             drawing_line <= 0;
>>         end
>>     end else if (start_line) begin
>>         ... grab input parameters into registers and start counter ...
>>         drawing_line <= 1;
>>     end
>> end
>>     
>
> How do you reset start_line? If I try to set it, iverilog complains that it's 
> a wire & not a reg... And if I don't set it, isn't the line going to start 
> drawing again as soon as drawing_line is reset?
>
> H
>   

Let's see if I can answer this.  I assume the start_line is an input. 
The client hardware must at /some/ point de-assert start_line, at least
before the next line.  Why not require that the client de-asserts it at
the next cycle after asserting it?  Most probably the client wants to
continue with something else, so sooner is better.

To complicate things a bit, I think this module must also have a busy
output, since the execution time is not constant.  To also allow
multiple clients, we could allow a client to set start_line while busy
is still set (due to any of the clients).  In that case the client must
wait for busy to go low, then de-assert start_line on the next cycle. 
This, of course, requires some extra logic in between to schedule work
from multiple clients, but it could have the same interface as the
single client case.

OTOH, if you don't want to pose the next-cycle de-assert restriction,
you could introduce a new register for it, or interface the start_line
with something line the following (untested) code

===clip===
module one_cycle_assert(clock, start_line, start_line_out);
    input clock;
    input start_line;
    output start_line_out;

reg start_line_out;
reg waiting_for_0;
always @(posedge clock) begin
    start_line_out = 0;
    if (waiting_for_0) begin
        if (!start_line)
            waiting_for_0 <= 1'b0;
    end
    else if (start_line) begin
        start_line_out = 1'b1;
        waiting_for_0 <= 1'b1;
    end
end
===clip===

Now, I'll leave it to the experts to criticize my suggestions, maybe I
learn something too.

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