On 7/18/06, James Richard Tyrer <[EMAIL PROTECTED]> wrote:
Timothy Miller wrote:
> On 7/18/06, James Richard Tyrer <[EMAIL PROTECTED]> wrote:
>> Timothy Miller wrote:
<SNIP>
> Actually, I was talking about the routing delays from an internal FPGA
> SRAM to a single layer of logic, back to the SRAM. This is all
> internal. You can run logic very fast in the FPGA, but the SRAM
> blocks tend to cause routing issues.
Oh Well! Sorry, I don't know any way to speed that up except to use
shorter traces. :-)
Did think of a semi-relevant question:
Can you use a FPGA like you would use an old style PLA [*not* PAL]
(later called a FPLA or FPLS), which were specifically designed to
implement a state machine?
Well, yeah, but the logic cells are somewhat more generalized.
OTOH, if you have enough gates, it is faster to use the desired output
as part of the state code (then you don't need to decode) although this
usually requires more states (and the extra ones are all illegal states).
I typically do this.
There used to be software to convert a state machine to a PAL logic
design -- probably still exists?? There is no decode with a PAL based
state machine. If you needed decode, you had to use another PAL.
I always just code it directly.
I haven't looked at ISE enough to know if it does this. It probably does.
Apparently, there are lots of IDE tools provided by Xilinx that I
don't use. One reason is that I've never bothered to look. The other
is that I like to write portable code.
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