On 7/20/06, Nicolas Boulay <[EMAIL PROTECTED]> wrote:
Just a think. Few years ago, i add look to DRAM technology and to
improve speed they tend to use interlaced bank access (RDRAM,...).
Banks represent only 2 bits in the address buses of DDR. Usually bank
are represented by MSB bit.
In the other hand, GPU will access large amount of linear data (screen
refresh, complete texture, ...). So if you put the bank in the LSB of
the address bus you could always interleave access and mask the CAS
latency. Am i right ?
I suppose, but only if you know far enough in advance. Can you give a
specific example of how you think it would work?
But honestly, I think that we'd quadruple the size of our state
machine, having to keep track of each bank, and then coordinate them
(because there's only one command bus).
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