On 7/19/06, Nicolas Boulay <[EMAIL PROTECTED]> wrote:
DDR interface are design to be pipelinable. You could often mask wait state with command for the next read or write. On SoC design, the usual data traject is from core to memory and memory to core, there is very few transfert between cores. So usually, the DRAM controller use many input. 4 buses usually for a single memory bank. Then the controller could interlaced the command. Each buses head generate instructions, then you need a unit that mixed or remove instruction to increase the performance.
I suspect you're referring to the fact that you can transfer data on one bank while another is being precharged or activated. I did some calculations on that (years ago), and especially for graphics, the performance advantage is trivial. It's not worth the extra logic. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
