Petter had a good question, and we felt that it would be good to share
this with others interested in FPGA design....
Presently the CPU
will start running right after reset is de-asserted, essentially playing
roulette with the well-being of anything it has access to. What's the
preferred way of bootstrapping the CPU with an image? My current
thoughts are
* Program the CPU while reset is held down. I suspect this is a
misuse of reset, though internally in the CPU I think the
reset-logic would fit well.
* Add a signal which enables/disables the entire pipeline. This
allows us to stall the CPU in case we have to deal with resource
congestion.
* Keep it as it is. The CPU can be bootstrapped by asserting
do_upload before releasing reset, but there is no way to stall it.
Petter
Here's another option that I like to use:
The reset into the CPU is not the global reset but rather a bit in a
config register. The global reset causes this reset to be asserted
(by initializing the register to zero), and the CPU doesn't wake until
we change that bit. This way, we can start and stop it at will.
Moreover, the synthesizer will treat the registered reset as any other
async reset, so we don't use any extra logic for it. Of course, with
this approach, there is no "pause". Stopping it kills the state and
causes it to completely restart.
Since the program file is dual-ported, we can always write to it while
it's running, and from a different clock domain, which has its
benefits. But if we take advantage of this state bit, we can give the
CPU a way to read/write its own program file. You could, therefore,
only write the program file while the CPU was halted. I wouldn't make
this any kind of priority -- a harvard architecture is nothing to be
ashamed of. :)
--
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
--
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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