Thanks for the info on the BRAMs, that sounds convenient. We are of
course making a CPU which should also work on ASIC, so I don't think it
hurt that we decided to solve the problem. After a suggestion from Tim,
I changed the bootstrapping logic so that the CPU's reset is local and
will be asserted during programming. A global reset will assert the
CPU's reset, which will only be de-asserted after the CPU is programmed.
It's not much extra logic, but we could `ifdef it out if we use the
Xilinx built-in image loading.
_______________________________________________
Open-graphics mailing list
[email protected]
http://lists.duskglow.com/mailman/listinfo/open-graphics
List service provided by Duskglow Consulting, LLC (www.duskglow.com)
