> Presently the CPU > will start running right after reset is de-asserted, essentially playing > roulette with the well-being of anything it has access to.
I gather that the microcode is stored in BRAM. The BRAM data can be perfectly initialized on the spartan3 at startup, so there'd be no roulette with a carefully crafted initialization data (a bootstrap loader if you can afford such complexity). Or am I missing something ? Xilinx provides ways to very easily manage changing the init data without recompiling the whole bitstream, so this is really easy to manage. If you can afford the bootstrap loader, this is not even an issue. But a global enable on the whole CPU, as you're suggesting, would presumably not cost you much, as Xilinx registers have a special enable wire IIRC. JB _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
