That's a great page, Mark. There's a lot you can see there too, like it demonstrates clearly things about routing, especially to/from pins.
As for Xilinx, I think I've kinda gotten used to it over time. I have adapted my coding style so that I am more likely to get the logic I intend. In general, the rule of thumb I apply to chip design is that the more you try to make the synthesizer infer (rather than telling it directly), the more likely you are to get suboptimal results. In order to be able to complete a design in a reasonable time, you have to strike a balance. I use the synthesizer and timing analysis as a profiler, so I know where to concentrate my optimization effort. On 8/31/07, Farhan Mohamed Ali <[EMAIL PROTECTED]> wrote: > Thanks! So it seems to me like this compiler is a bit more consistent > than the xilinx one. On xilinx i get rather different timing and > utilization results between v2 and v3, even though they are logically the > same. > > On Fri, August 31, 2007 11:19 am, Mark said: > > I've posted a run-down of the multipliers so far (any important ones > > missing?) at http://jarvin.net/opengraphics/. This includes photos of > > the most critical path post-PAR. > > _______________________________________________ Open-graphics mailing > > list [email protected] > > http://lists.duskglow.com/mailman/listinfo/open-graphics List service > > provided by Duskglow Consulting, LLC (www.duskglow.com) > > > > > > _______________________________________________ > Open-graphics mailing list > [email protected] > http://lists.duskglow.com/mailman/listinfo/open-graphics > List service provided by Duskglow Consulting, LLC (www.duskglow.com) > -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
