Petter Urkedal wrote:
There was a couple of bugs in the code I submitted, so here is a fixed version which is also extended to 32x16->48 multiply. It runs in 16 cycles to produce a partial result which is fixed up with a 32 bit add.
For this code, Synplify for Lattice tries for 200MHz and achieves 213MHz. Map reports 78 slices (109 4LUTs). PAR (inexplicably) tries for 548MHz and achieves 363MHz (the critical path is only two levels of logic). This seems a little fishy, but I'm not well-versed enough with Lattice's tools to give you a more detailed analysis as yet. I've really got to get down to reading Lattice's documentation...
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