There was a couple of bugs in the code I submitted, so here is a fixed
version which is also extended to 32x16->48 multiply. It runs in 16
cycles to produce a partial result which is fixed up with a 32 bit add.
module mul32x16ser_helper(clock, start, x, y, za_o, zb_o);
input clock, start;
input[31:0] x;
input[15:0] y;
output[47:0] za_o;
output[31:0] zb_o;
reg[31:0] x_r;
reg[14:0] y_r;
reg[30:0] s;
reg[31:0] c;
reg[15:0] v;
integer i;
always @(posedge clock) begin
if (start) begin
x_r <= x;
y_r <= y[15:1];
s <= x[31:1] & {31{y[0]}};
c <= 0;
v <= {x[0] & y[0], 15'b0};
end else begin
v[14:0] <= v[15:1];
{c[0], v[15]} <= (x_r[0] & y_r[0]) + c[0] + s[0];
for (i = 1; i < 31; i = i + 1)
{c[i], s[i - 1]} <= (x_r[i] & y_r[0]) + c[i] + s[i];
{c[31], s[30]} <= (x_r[31] & y_r[0]) + c[31];
y_r <= {1'b0, y_r[14:1]};
end
end
assign za_o = {s[30:0], v};
assign zb_o = c;
endmodule
module test();
reg clock, start;
reg[31:0] x;
reg[15:0] y;
wire[47:0] za;
wire[31:0] zb;
always #5 clock <= !clock;
mul32x16ser_helper mul(clock, start, x, y, za, zb);
parameter xc = 4114818791;
parameter yc = 61519;
wire[47:0] z = za + {zb, 16'b0};
initial begin
$monitor("%d za = %d, zb = %d, z = %d", $time, za, zb, z);
clock <= 1;
start <= 1;
x <= xc;
y <= yc;
#1000;
start <= 0;
#150;
$display("Result should be %d", xc*yc);
$finish;
end
endmodule
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