--- [EMAIL PROTECTED] wrote:
module IC74138(
input [3:0] select,
input G1_bar,
input G2_bar,
input G,
output reg [7:0] out);
always @(select, G1_bar, G2_bar, G) begin
if (G1_bar==1 || G2_bar==1 || G==0) begin
out = 8'b11111111;
end else begin
case (select)
0: out = 8'b11111110;
1: out = 8'b11111101;
2: out = 8'b11111011;
3: out = 8'b11110111;
4: out = 8'b11101111;
5: out = 8'b11011111;
6: out = 8'b10111111;
7: out = 8'b01111111;
endcase
end
end
endmodule
Here's another way to do it. This one is shorter, which isn't really
a good thing for HDL. Explicit is better. A good synthesizer will
make the above give you very good results. However, for the sake of
interest, here's a more concise way:
module unpreferably_IC74138(
input [3:0] select,
input G1_bar,
input G2_bar,
input G,
output reg [7:0] out);
wire [7:0] intermediate = (!G1_bar && !G2_bar && G) << sel;
assign out = ~intermediate;
endmodule
Verilog has this concept of "natural size", which is a set of rules
that dictate the number of bits in an expression. Sometimes, the
expressions don't fully specify the width. Using the intermediate
above forces the left-shift of a 1-bit quantity to come out as an
8-bit number.
--- End of Quote ---
I posted to the wiki a module very similar to the unpreferably_IC74138.
I understand that it is harder to read (though makes more sense once you
realize what the 74138 does), but I was under the impression that it
would probably run faster or use less resources in actual hardware. Is
there any way to determine the method that will run faster besides spending
45 minutes converting it to run in ISE or making an educated guess? I would
assume that the shifting version would run slower, due to more logic levels,
but use many fewer gates.
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