On 11/6/07, Patrick McNamara <[EMAIL PROTECTED]> wrote: > My reason for doing this is that if we put together a library of gates > and chips like this, the you could take a gschem netlist and generate > Verilog RTL for the circuit (assuming it's all digital of course). Also
Excellent idea. Let's do it this way. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
