On 2007-11-30, Timothy Normand Miller wrote: > > Though this need some work on the timing. I'm only testing with the > > Xilinx xst tool targeting Spartan 3, which gives 79.5 MHz. Ripping out > > the shifter and adder from the ALU, I get 94.5 MHz, so I presume we > > could pipeline those operations into the MEM/IO unit if we are willing > > to give up register forwarding for those ops. > > I'm really good with timing-related stuff, so I can help with that.
Yes, I suspected so :-) > At the moment, the primary goal is correctness. We can put off SOME > performance issues until somewhat later in the process. In > particular, if you optimize too early, you obscure the semantics of > what you're doing, making it much harder to debug. I've been worried that we'd still had to change the semantics in order to reach timing goal. If you thing it looks realisable, then let's carry on under that assumption. > This is why I did the PCI controller in stages. [...] Thanks for the explanation. It's good to know the method of postponing optimisations kind of works also in hardware design with a lot harder constraints then in software. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
