On 11/28/07, Petter Urkedal <[EMAIL PROTECTED]> wrote: > On 2007-11-27, Timothy Normand Miller wrote: > > Here are the things we have: > > [...] > > - A synthesizable nanocontroller (HQ) > > Though this need some work on the timing. I'm only testing with the > Xilinx xst tool targeting Spartan 3, which gives 79.5 MHz. Ripping out > the shifter and adder from the ALU, I get 94.5 MHz, so I presume we > could pipeline those operations into the MEM/IO unit if we are willing > to give up register forwarding for those ops.
I'm really good with timing-related stuff, so I can help with that. At the moment, the primary goal is correctness. We can put off SOME performance issues until somewhat later in the process. In particular, if you optimize too early, you obscure the semantics of what you're doing, making it much harder to debug. This is why I did the PCI controller in stages. I developed a simulation-only model and tested the heck out of it to make sure that it was logically correct. Only then did I obfuscate it horribly to make it meet timing. Mind you, if there's a bug in the synthesis version, it'll be hard to debug, but we have no choice there. With other logic, you can afford to run it at half speed for a while until you know it's correct then start hacking in optimizations. Even then, you want to do them gradually and test the consequences of each change. > > > Who's in? This is really important, so I hope I can get some of the > > more hesitant people involved. > > I'm in on issues involving the HQ. Thank you! And thanks also to the others who have already offered to help! -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
