On Fri, 30 Nov 2007 14:44:12 -0500
"Timothy Normand Miller" <[EMAIL PROTECTED]> wrote:
> Oh, BTW, even for the most experienced chip designers, reading these
> timing diagrams can be very time-consuming and frustrating. At the
> very least, it's extremely tedious. It has advantages and
> disadvantages over, say, gdb, because you can dig down into the logic
> and in to the past. Also, simulation is one of the most important
> things you can do. Just because we're doing FPGAs doesn't mean we can
> just "compile it and try it." The simplest bugs can make something so
> nonfunctional that you have no hope of finding the problem without
> access to internal signals.
A little warning here. Unlike with software, it's always possible
to fry your hardware if you have a bug in your verilog code at
the wrong place (ever tryed what happens if two drivers try to set
the same line to different levels?).
So, simulate well :-)
Attila Kinali
--
Linux ist... wenn man einfache Dinge auch mit einer kryptischen
post-fix Sprache loesen kann
-- Daniel Hottinger
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