On Sat, 26 Jan 2008 20:19:46 +0100
"Reimar Döffinger" <[EMAIL PROTECTED]> wrote:
> > You're entitled to your opinion, but I encourage others to try out the
> > software and form their own. I've found it perfectly adequate for my SoC
> > designs & research. It's used by another research group at my university
> > for multi-FPGA molecular dynamics simulations. I was just talking with a
> > guy yesterday who's doing 600MHz DSP designs for V5 with ISE.
>
> Hmm.. maybe those are hardware/EE guys? I always get told that nobody
> else tries to use highlevel-constructs like I do (and using VHDL, maybe
> support for that is a bit worse).
I realized that too. But that's also something you learn normaly
in VLSI classes, that most synthesizer are not able to make anything
out of more highlevel constructs, although for anyone trained in
the field the outcome would be clear. I think this is a limitation
given by the problem size. Unlike with compilers, where the problem
of producing code is also NP complete, with synthesis you have the
additional restrictions that you have to make it fast enough and
still fit into a chip/FPGA you have to use. Not to talk about that
the problem space is a lot larger due to more possibilities to
choose from. So i cannot really blame the synthesis tools for this
problem of not being able to synthesize high level constructs.
Attila Kinali
--
Linux ist... wenn man einfache Dinge auch mit einer kryptischen
post-fix Sprache loesen kann
-- Daniel Hottinger
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