Excellent. I just have a couple of comments.
;; PCI Ports
;; =========
let _PCI_B = -0x20 ; base address for PCI ports
;; Master Command
let PCI_M_CMD = _PCI_B + 0x00 ; out - direction and count
let PCI_M_CMD_FREE = _PCI_B + 0x01 ; in - number of commands we can write
;; Master Write
let PCI_M_WRITE_FREE = _PCI_B + 0x02 ; in - how many data words we can write
let PCI_M_WRITE_DATA_0000=_PCI_B + 0x10 ; out - 16 ports for data word, where
; lower 4 address bits are byte enables
let PCI_M_WRITE_DATA_1111 = PCI_M_WRITE_DATA_0000 + 15 ; for convenience
* I was thinking about it, and for PCI master, you're right. We
definitely need a zero so we can do a null transaction on the bus.
;; Master Read
let PCI_M_READ_DATA = _PCI_B + 0x04 ; in - data word
let PCI_M_READ_COUNT = _PCI_B + 0x05 ; in - number of words available to read
;; Target Write
let PCI_T_WRITE_COUNT = _PCI_B + 0x08 ; in - number of words in write queue
let PCI_T_WRITE_ADDR_FL = _PCI_B + 0x09 ; in - address and flags for a write
let PCI_T_WRITE_DATA = _PCI_B + 0x0a ; in - data of write word
* The way we queue writes for the bridge is that there's an address
followed by data. But since HQ is 32-bit, there aren't enough bits to
detect that. But maybe we should think about that. It would be nice
if the protocol to fetch PCI writes were more similar to the protocol
to push them on to the bridge.
;; Target Read
let PCI_T_READ_PENDING = _PCI_B + 0x0b ; in - nonzero if pending read
let PCI_T_READ_ADDR = _PCI_B + 0x0c ; in - the one address that is pending
let PCI_T_READ_DATA = _PCI_B + 0x0d ; out - where we write the one word
;; Memory Ports
;; ============
let _MEM_B = -0x40 ; base address for memory ports
let MEM_READREQ_FREE = _MEM_B + 0x00 ; in - Free slots in command pipe.
let MEM_READREQ_ADDR_TRIG=_MEM_B + 0x01 ; out - First address to read.
let MEM_READREQ_COUNT = _MEM_B + 0x02 ; out - Number of words to read.
let MEM_READREPLY_DATA = _MEM_B + 0x03 ; in - Data stream from memory.
let MEM_READREPLY_AVAIL = _MEM_B + 0x04 ; in - Number of words in FIFO.
let MEM_WRITE_ADDR = _MEM_B + 0x05 ; out - Start address.
let MEM_WRITE_FREE = _MEM_B + 0x06 ; in - Free slots in output FIFO.
let MEM_WRITE_DATA_0000 = _MEM_B + 0x10 ; out - 16 ports for data stream, where
; lower 4 address bits are enables.
let MEM_WRITE_DATA_1111 = MEM_WRITE_DATA_0000 + 15 ; for convenience
* All write addresses, read addresses, read counts, and write data go
into one queue. Obviously, they need different ports in order to set
the other flags in the command word, but since there's only one queue,
then there should be only one "free" port. I've also been thinking
about the 0000 write. At first, I thought it should be there but do
nothing. Now, I think it's a good way to insert a "dead" write into
the stream, like a convenient way to skip a word or two while
advancing the auto-increment, although issuing an address command
doesn't really waste any time by comparison.
* There are three bus commands. They are:
parameter b_addr = 1;
parameter b_rcount = 2;
parameter b_write = 3;
So, you can set addresses all you want. They take up queue space, but
all they do is set the address in the S3. rcount triggers a read, and
write issues a write word (and we can think of it as generally
stateless except that we have to make sure the address is right). If
you know what rcount and write commands are going to do to the address
counter in the S3, there may be circumstances where you can skip the
address command, although I wouldn't generally recommend certain
combinations simply because it's more of a pain sometimes to keep
track than to just issue another address.
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