I'd like to work in integrating HQ today or tomorrow. Do we have a summary somewhere of the ports and how we're going to handle address, byte enables, target, count, etc?
I'm going to start with the fifos. To begin with, it'll just be those in a module, wired for bypass only, and then we can insert HQ into there next. Here's what we have: pci command/write fifo -> HQ -> bridge command fifo bridge read data fifo -> HQ -> pci read data fifo Am I missing anything? I need to go look up the ports. We have ports defined for a single out-standing read. That won't work for a block of reads, though. Do we need it for anything? There are other comments I've made about stuff I'm going to forget. For instance, we need to make sure that timeouts work right. I'm going to go through the discussions, but I could use some help with those details. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
