On 2008-07-23, Timothy Normand Miller wrote:
> I was thinking that we should have one port that indicates type
> (address, read count, write data) and byte enables or target. The
> other port would be the data/address port and also dequeue.
Done.
> Something I just realized: We need an enable/disable for the data
> cache in the address decoder. For memory accesses, it has a 16-word
> cache that we need to bypass when HQ is running. Sometimes we want to
> leave it on. For instance, in text mode, it doesn't hurt anything.
As far as I can see from pci_address_decode.v, this is used for target
reads, right? So, as long as reads are pure, it doesn't hurt to leave
it on. Of course, HQ can always yield some side-effect on read, but is
that useful? If not, we could maybe reformulate the target read ports
of HQ to allow transmitting more than a single word, and thus benefit
from the cache.
> Another way to do it is to encode the target into the port, like we
> did with byte enables. There are only two (maybe three, more on this
> later) targets that can be accessed via the bridge, memory and engine.
> So we just need two address ports:
> MEM_SEND_ADDR_MEM
> MEM_SEND_ADDR_ENG
Done, and we just leave space for a third port.
> Everything else stays the same.
Well, I wasn't quite satisfied, but we can go back to the previous
version, if you like. I assumed the master command queue is the same as
the master write queue, so that the _FREE ports should be the same.
Thus, I did something similar to the memory port, including the names.
Now, all enqueuing ports are named _SEND and all dequeuing ports are
named _RECEIVE.
;; PCI Target Numbers
let PCI_TARGET_CFG = 0 ; (not seed by HQ) configuration
let PCI_TARGET_ENG = 1 ; engine
let PCI_TARGET_MEM = 2 ; memory
let PCI_TARGET_PROM = 3 ; (not seen by HQ)
let PCI_TARGET_IO = 4 ; IO
;; PCI Ports
;; =========
let _PCI_B = -0x20 ; base address for PCI ports
;; Master Command
let PCI_M_CMDQ_FREE = _PCI_B + 0x00 ; in - number of commands we can write
let PCI_M_SEND_CMD = _PCI_B + 0x01 ; enq - direction and count
;; Master Write
let PCI_M_SEND_DATA_0000= _PCI_B + 0x10 ; enq - 16 ports for data word, where
; lower 4 address bits are byte enables
let PCI_M_SEND_DATA_1111= PCI_M_SEND_DATA_0000 + 15 ; for convenience
;; Master Read
let PCI_M_READQ_COUNT = _PCI_B + 0x04 ; in - number of words available to read
let PCI_M_RECEIVE_DATA = _PCI_B + 0x05 ; deq - data word
;; Target Write
let PCI_TW_COUNT = _PCI_B + 0x08 ; in - number of words in write queue
let PCI_TW_INFO = _PCI_B + 0x0a ; in - type, target, byte-enables
let PCI_TW_INFO_TARGET_SHIFT = 29
let PCI_TW_INFO_TARGET_MASK = 0xe0000000
let PCI_TW_INFO_TYPE_MASK = 0x03000000
let PCI_TW_INFO_TYPE_ADDR = 0x00000000
let PCI_TW_INFO_TYPE_RCOUNT = 0x01000000
let PCI_TW_INFO_TYPE_WDATA = 0x02000000
let PCI_TW_INFO_ENABLE_MASK = 0x0000000f
let PCI_TW_RECEIVE = _PCI_B + 0x0b ; deq - address or written data
;; Target Read
let PCI_TR_PENDING = _PCI_B + 0x0c ; in - nonzero if pending read
let PCI_TR_RECEIVE_ADDR = _PCI_B + 0x0d ; deq - the one address that is pending
let PCI_TR_SEND_DATA = _PCI_B + 0x0e ; enq - where we write the one word
;; Memory Ports
;; ============
let _MEM_B = -0x40 ; base address for memory ports
let MEM_CMDQ_FREE = _MEM_B + 0x00 ; in - free slots in command pipe
let MEM_SEND_ADDR_MEM = _MEM_B + 0x08 ; enq - address for memory read or write
let MEM_SEND_ADDR_ENG = _MEM_B + 0x09 ; enq - address for engine read or write
let MEM_SEND_READ_COUNT = _MEM_B + 0x0f ; enq - do a read of given word count
let MEM_SEND_DATA_0000 = _MEM_B + 0x10 ; enq - 16 ports for data stream, where
; lower 4 address bits are enables
let MEM_SEND_DATA_1111 = MEM_SEND_DATA_0000 + 15
let MEM_READQ_AVAIL = _MEM_B + 0x02 ; in - number of words in FIFO
let MEM_RECEIVE_DATA = _MEM_B + 0x03 ; deq - data stream from memory
;; [1] http://readlist.com/lists/duskglow.com/open-graphics/1/6252.html.
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