On Thu, Jul 24, 2008 at 4:31 PM, Petter Urkedal <[EMAIL PROTECTED]> wrote:
> I see the point, thanks. I may ask about details later, but this should > suffice for the port definitions. So, I reverted the _FREE port > unifications for the master and some of naming. Should I commit > hqio.asm, or do you prefer to wait till nail down the port numbers > (i.e. after the Verilog is written)? Go ahead and commit it. We can always revise it. I wonder if the target read pending port is really necessary. If a read comes in, then we get a read address appearing in the TW queue, and when we pop that, we get the address, and the next word we pop is the count. It could be valuable in weird cases where we popped the read, but it's never been serviced, but we need to make sure we pop from TW. One thing to be careful about is retries on PCI. If it times out, the bus is released, then the other master retries, which means we get another request. I've had to put in logic to ensure that duplicate requests are not passed on. We need to make sure it's complete. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
