Nicolas, your idea regarding LIW instructions has merit except for one problem: Register file bandwidth.
With very clever pipeline organization, we can read two regs at once, and when the write-back occurs, it is always timed with a non-conflicting bank. Note that even in ASICs, SRAM blocks are almost always dual-ported. Now, if we were to have separate FP and INT reg files (which CPUs do for bandwidth reasons), that would be fine, but now that doubles the SRAM resources we need for a core in a way that isn't economical, since the int registers will go underutilized. So for very practical reasons, every instruction must have two register inputs and one register output. There are very few combinations that would work otherwise. Only memory write and branch have no target register. They could be combined, sometimes, with a single-input ALU op, but we haven't decided that we'll have any of those. How often is it useful to combine a memory write with an FPNEG? Do we really want to spend the extra logic to optimize such a low-probability case? -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
