I had to disappear for a while... graduating, parents visiting, having a baby... been kinda hectic.
Anyhow, I added some code to the repo. FPGA-cache.v is, so far, just the tag array portion of a set-associative cache. It expects to use a 256x72 block RAM to store address tags. At the moment, the code can only decode, and I put in no way to update the tags, but this gets the general idea across. Then there's pipelinedaddsub.v. As discussed earlier, we want lots of positive slack, so this is being pipelined more than strictly necessary but it doesn't matter since we have a really long pipeline anyhow. And also, if someone could debug this for me. It's been a long time since I looked at this code, and I'm not sure if I got the logic right. It's one thing to pipeline an adder or subtractor, but combining them gets weird because of carry/borrow bit means different things depending on what you're doing. Finally, I updated the pipeline diagram. I'm open for comment on that as well. Thanks. -- Timothy Normand Miller, PhD http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
