On Sun, 24 Jun 2012 19:56:36 -0400, Timothy Normand Miller wrote:
On Sun, Jun 24, 2012 at 4:56 PM, <[email protected]> wrote:
Hi !
<snip>
ok, here is the key trick, but it's in VHDL.
Don't write two adds if you don't want them.
Instead, extend the width of the source vectors by one LSB,
set one LSB to 1 and the other is the conditional carry-in.
Then, for the output, just drop the added LSB.
The synthesizer will quietly optimise this pseudo-carry-in.
*smacks forehead* After all these years, I never thought of that,
although it seems obvious now. Sheesh. Is that a consequence of
being daft or just being self-taught? :)
I suppose : self-taught :-)
Well, anyhow, I FEEL dumb now. :)
hey, that's the sweetest moment,
when the light finally shines on you :-)
I was getting worried because i had NEVER seen
a computer that had a separate add and sub unit.
Unless for some niche DSP things.
Similarly, you can get the carry out by appending a cleared MSB to
both
operands.
That one I knew. :)
Although, interestingly, the Verilog tools are happy to take two
8-bit
addends and produce a 9-bit result with carry.
VHDL is quite strict, so at least it's rather predictable.
But as long as it works...
I see no need of multiplexing an adder and subber results :-)
So what you're saying is that with a trick in the low bit and a 1's
complement, I can can do an addsub? I'll have to tinker with that.
Well that's what I do, I've never see such a code before but
I suppose that's how others do it. There can't be that many ways after
all.
For the signed/unsigned comparison, have a deeper look at the code
that computes compare_signed, ActualB and ActualA. It's just XORs,
as promised.
I'll have to spend some time reading that code. I'm not so good at
reading VHDL, though.
I'll try to make a logic diagram one day,
until then there is a little explanation at the bottom of this email.
I would like to know more about this. Can you provide a longer
explanation? With an overflow bit, (A<B) is a single instruction
change, depending on whether A and B are signed or not. Without an
overflow bit, how is this handled?
Without overflow, the idea is
(for unsigned operands) :
CMPU operand1, operand2
if carry, DO something
for signed operands, just use CMPS instead
(it xors the MSB of both operands)
XORs them with what? Anyhow I assume I'll discover that in the code
to that CPU.
* ActualA gets its MSB toggled if a signed compare instruction is being
decoded :
ActualA <= ( SI4(YASEP_SIZE-1) xor compare_signed )
& SI4(YASEP_SIZE-2 downto 0);
* ActualB gets its MSB toggled too, unless it's a signed comparison
(because of weird decoding collisions),
the other bits are toggled in case of sub, cmps, cmpu, and some
ROP2 instructions :
ActualB <= ( SND(YASEP_SIZE-1) xor (Addsub and (not compare_signed))
)
& ( SND(YASEP_SIZE-2 downto 0) xor (YASEP_SIZE-2 downto 0
=>Addsub));
That's all.
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