On Mon, Jun 25, 2012 at 2:59 AM, <[email protected]> wrote: > > > I suppose : self-taught :-)
You are too kind. :) > > >> Well, anyhow, I FEEL dumb now. :) > > > hey, that's the sweetest moment, > when the light finally shines on you :-) > > I was getting worried because i had NEVER seen > a computer that had a separate add and sub unit. > Unless for some niche DSP things. Having thought about this, I think that even if there were an advantage to separating them, it would be so minor as to be useless. > > >>> Similarly, you can get the carry out by appending a cleared MSB to both >>> operands. >> >> >> That one I knew. :) >> >> Although, interestingly, the Verilog tools are happy to take two 8-bit >> addends and produce a 9-bit result with carry. > > > VHDL is quite strict, so at least it's rather predictable. > But as long as it works... There are a million things I like about VHDL. It's the syntax that drives me nuts and the fact that I have to jump through hoops to do simple things. For instance, I recall that I had trouble with concatenating some bits, converting them to an integer, and then using that as an index into an array. Verilog, on the other hand, is sloppy, at least if you're the sort that prefers strictly-typed languages. Verilog expressions are more compact, like C, while VHDL expressions are very verbose, like Ada. If you want to type less, use Verilog. If you want to avoid syntax that's so terse it can be confusing, use VHDL. :) Over the years, Verilog has been adding a lot of VHDL features. I would like data structures, for instance, and Verilog's "generate" feature is limiting and cumbersome. I could get used to coding in VHDL. But anyhow, for me, one of the biggest problems is that I don't know of any good FOSS VHDL tools. I simulate using Icarus Verilog. >>> Without overflow, the idea is >>> (for unsigned operands) : >>> >>> CMPU operand1, operand2 >>> if carry, DO something >>> >>> for signed operands, just use CMPS instead >>> (it xors the MSB of both operands) >> >> >> XORs them with what? Anyhow I assume I'll discover that in the code >> to that CPU. > > > * ActualA gets its MSB toggled if a signed compare instruction is being > decoded : > > ActualA <= ( SI4(YASEP_SIZE-1) xor compare_signed ) > & SI4(YASEP_SIZE-2 downto 0); > > * ActualB gets its MSB toggled too, unless it's a signed comparison (because > of weird decoding collisions), > the other bits are toggled in case of sub, cmps, cmpu, and some ROP2 > instructions : > > ActualB <= ( SND(YASEP_SIZE-1) xor (Addsub and (not compare_signed)) ) > & ( SND(YASEP_SIZE-2 downto 0) xor (YASEP_SIZE-2 downto 0 > =>Addsub)); > For some reason, I find this hard to penetrate. I'm going to have to print it out and study it. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
