On Sun, 24 Jun 2012 21:26:59 -0400, Timothy Normand Miller wrote:
I had to think a little bit, and here's what I came up with:
<snip>
wire [31:0] b0 = {32{sub}} ^ b;
wire [33:0] b1 = {1'b0, b0, 1'b1};
wire [33:0] a1 = {1'b0, a, Cin};
ouch...
the choices of "b1" and "b0" as "wire" names
is confusing me, as it took a while to understand the syntax :-D
Thanks, Yann, for teaching me basic math. :)
thanks for teaching me Verilog :-)
Yann
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