On Mon, Jun 25, 2012 at 3:06 AM, <[email protected]> wrote: > On Sun, 24 Jun 2012 21:26:59 -0400, Timothy Normand Miller wrote: >> >> I had to think a little bit, and here's what I came up with: > > <snip> > >> >> wire [31:0] b0 = {32{sub}} ^ b; >> wire [33:0] b1 = {1'b0, b0, 1'b1}; >> wire [33:0] a1 = {1'b0, a, Cin}; > > ouch... > the choices of "b1" and "b0" as "wire" names > is confusing me, as it took a while to understand the syntax :-D
Oh, yeah. That was a really poor choice on my part. Sorry about that. "b0" is a signal bus, while "1'b0" is a single-bit binary value of zero. > > >> Thanks, Yann, for teaching me basic math. :) > > thanks for teaching me Verilog :-) > > Yann -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
