On 15/07/2023 13:13, Tommy Murphy wrote:
Thanks Tomas.
I wonder if playing with ACTLR[20:16] aka DISDI has any impact on this
test? I don't think that dual issue can be completely disabled in case
it's a factor here? Maybe set it to 0x3F and see if that makes any
difference?
https://developer.arm.com/documentation/dui0646/a/Cortex-M7-Peripherals/System-control-block/Auxiliary-Control-Register?lang=en
Good idea. But unfortunately no luck on r1p0.
I tested all DISDI bits set, then DISBTACREAD set and then all DISDI and
DISBTACREAD set.
T
