Hi Rolf,
Am 05.12.23 um 12:37 schrieb Rolf | Onethinx:
Hi,
I am looking to updating the OpenOCD flash drivers for Infineon PSoC6 and
syncing with the latest Infineon branch.
I have an issue with chip SRST reset which seems to work differently on several
adapters (CMSIS-DAP / KitProg / JLink). For the cases where the CPU is in
sleep, a SRST reset is needed before programming (to take the CPU out of
sleep). I looked through the reset_config command but there doesn’t seem to be
a simple command which issues as SRST pulse before programming. The command
‘reset_config connect_assert_srst srst_gates_jtag’ seems to work differently on
each device. Is it possible to add a SRST pulse before init without the need of
a custom reset handler (I guess this is mandatory for devices in Sleep mode)?
If I understand your use case correctly, it is more or less some special
workflow:
- you wont to write something to a flash storage using JTAG interface
- the device is unknown state, so it should be reset by using SRST, before
something (currently
unclear, should it be done before starting JTAG communication with the debug
port, or before CPU can
be accessed).
Since resetting things is a more or less destructive procedure, it is not
compatible with every
workflow. For example, SRST before hotpluggable debug session is not
recommended.
If the question is, can SRST be done by default to all targets, the answer is -
no.
If I misunderstand your question, please rephrase it :)
--
Regards,
Oleksij
