Rolf, you can try with reset_config srst_only srst_nogate connect_assert_srst but this is not valid for every SoC, so give it a try.
You can find more details in OpenOCD documentation, but shortly this command will instruct OpenOCD to: 1) start and keep the SoC under reset 2) while the SoC is under reset, OpenOCD will try to set 'halt in reset vector' 3) when gdb attaches, the reset is removed and the CPU should halt at reset vector. The tricky point is 2). Some SoC during reset disables the JTAG port or disables the debug clock, so operation 2) will fail. I just tested it on a STM32F4, running this on command line: openocd -f board/st_nucleo_f4.cfg -c 'reset_config connect_assert_srst' -c init -c 'reset halt' and it halts at reset vector even when FW in flash reconfigures the JTAG pins of when all the clocks are off due to power saving or idle Antonio On Thu, Dec 7, 2023 at 4:40 PM Tommy Murphy <tommy_mur...@hotmail.com> wrote: > > > How can I implement an SRST procedure of let’s say 10mS assert > > Using the `adapter assert/deassert` and `sleep` commands maybe? > > https://openocd.org/doc/html/General-Commands.html#:~:text=Command%3A%20adapter%20assert%20%5Bsignal,%5Bsignal%20%5Bassert%7Cdeassert%20signal%5D%5D > https://openocd.org/doc/html/General-Commands.html#:~:text=Command%3A%20sleep%20msec%20%5Bbusy%5D > > >
