Hi Jorg, Thanks for the reply.
I tried what you suggested, and that has helped .. However, I still have some un-reliability related to the jtag speed setting. If I set to 500khz, I get to the reset vector ok, but do not get to the breakpoint at main, and the debugger goes off to the weeds. If I set to 50khz, I get to main ok, but reading variables etc at a breakpoint generates errors .. If I set to 20khz, I get perfect debugging no errors .. So, do I have incorrect clock settings, or maybe my hardware is flakey at high JTAG clock rates .. Any suggestions? What speed are you running at? .. And could you attach your .cfg file .. Thanks. Cheers, Bernie ------------------------------------------------------------------------------------------ Hiding the Truth with "Political Correctness" is the same as Lying ... BRM -----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of Jörg Fischer Sent: Wednesday, 13 October 2010 9:13 a.m. To: [email protected] Subject: Re: [Openocd-development] Problem getting reliable "reset init" on LPC1766 target. Am 11.10.2010 22:04, schrieb Bernard Mentink: >> # LPC2000 & LPC1700 -> SRST causes TRST reset_config srst_pulls_trst That does not work for me anymore since the "Cortex-M3 reset handling" patch is in. Have you tried "reset_config srst_only"? >> target remote localhost:3333 Here must be a "mon reset init". Otherwise, you'll have the "wrong" CCLK on "load". >> load >> mon reset init And you want to change this to a "mon reset halt" or your ADCs won't work. The bootloader initializes the calibration in the ADC. >> thb main -- J. Fischer _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
