On Tue, Oct 12, 2010 at 11:25 PM, Bernard Mentink
<[email protected]> wrote:
> Ok, thanks, although I still don't understand why the example
> LPC1768.cfg script has the OSC startup at 4Mhz, and states
> you then can use 4Mhz/6
> Which is roughly 500Khz ... But this doesn't work.

You're not using the latest master branch are you?

from target/lpc1768.cfg:

# Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
jtag_khz 10



> Do you, or anyone else, have a reset-init sequence
>(for the LPC1766/68) that sets the PLL and cranks up the clock?

Check out board/mcb1700.cfg

>
> Cheers,
> Bernie
>
>
> ------------------------------------------------------------------------------------------
> Hiding the Truth with "Political Correctness" is the same as Lying ... BRM
>
> -----Original Message-----
> From: Øyvind Harboe [mailto:[email protected]]
> Sent: Wednesday, 13 October 2010 10:02 a.m.
> To: Bernard Mentink
> Cc: Jörg Fischer; [email protected]
> Subject: Re: [Openocd-development] Problem getting reliable "reset init" on 
> LPC1766 target.
>
>> If I set to 20khz, I get perfect debugging no errors ..
>
> I have found that the JTAG clock needs to be *really* low when the system is 
> running off an RC oscillator. Once on a PLL, you can crank up the speed. This 
> was observed on an LPC1768, but also one other system I fail to recall 
> which...
>
> RCLK is implemented on some systems that have RC oscillators, but here I've 
> found the RCLK frequency to be unreliable.
>
> Why this would be, I have no idea...
>
> --
> Øyvind Harboe
> US toll free 1-866-980-3434 / International +47 51 63 25 00 
> http://www.zylin.com/zy1000.html
> ARM7 ARM9 ARM11 XScale Cortex
> JTAG debugger and flash programmer
>



-- 
Øyvind Harboe
US toll free 1-866-980-3434 / International +47 51 63 25 00
http://www.zylin.com/zy1000.html
ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash programmer
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