Yeah, I read that part of the manual before. In my opinion, there should probably be a patch to the arch manual as well. It is kind of odd to have a special register like r0 that isn't fully defined at the ISA level. Every other architecture that has a similar r0 == 0 has r0 hard-wired to zero.
---Matthew Hicks On Thu, Dec 15, 2011 at 3:53 PM, Stefan Kristiansson < [email protected]> wrote: > On 12/15/2011 11:15 PM, Matthew Hicks wrote: > >> The current or1200 implementation allows any value to be written to r0, >> which is supposed to always be 0. The following patch basically ignores >> all writes to r0. >> >> Index: or1200_rf.v >> ==============================**==============================**======= >> --- or1200_rf.v(revision 672) >> +++ or1200_rf.v(working copy) >> >> @@ -186,7 +186,7 @@ >> // >> // RF write data is either from SPRS or normal from CPU datapath >> // >> -assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw; >> + assign rf_dataw = (rf_addrw == 0) ? 32'b0 : (spr_valid & spr_write) ? >> spr_dat_i : dataw; >> // >> // RF write enable is either from SPRS or normal from CPU control >> >> >> Although I don't see anything wrong with doing what you are proposing, > allowing writes to r0 is actually not a bug. > The arch manual states: > > "R0 is used as a constant zero. Whether or not R0 is actually hardwired to > zero is > implementation dependent. R0 should never be used as a destination > register." > > Stefan >
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