On Fri, 2011-12-16 at 09:37 +0100, Jonas Bonn wrote: > On Fri, 2011-12-16 at 09:25 +0100, Olof Kindgren wrote: > > 2011/12/16 Matthew Hicks <[email protected]>: > > > Yeah, I read that part of the manual before. In my opinion, there should > > > probably be a patch to the arch manual as well. It is kind of odd to > > > have a > > > special register like r0 that isn't fully defined at the ISA level. Every > > > other architecture that has a similar r0 == 0 has r0 hard-wired to zero. > > > I agree with Matthews. Sure, we get another multi-purpose register, > > but I don't think it's worth the pain of not knowing if it's really > > zero > > > > We had this discussion a year ago. The spec is fuzzy on this, but it > seems that it's valid to use r0 as a general purpose reg, it's just a > bad(?) idea. It's a callee-saved register, though, to be certain. > > GCC, as it stands today, will never assign to r0 and will assume that it > always contains r0. That said, there's surely some arcane assembly code > that makes good use of this feature... in fact, I had some idea to try > to use it as temporary storage at the exception entry point (can't > recall whether that worked out or not). > > In any case, changing the spec isn't kosher, and hard-wiring to 0 isn't > compliant. It's weird, agreed, but it's probably correct as it stands > today.
Hmmm... the spec actually says: "Whether or not R0 is actually hardwired to zero is implementation dependent." That means, it MAY be hardwired to zero, so using it as a general-purpose register will fail on some implementations. I take back what I said... hard-wiring to 0 is compliant. That's actually disappointing... having r0 available for temporary storage at exception entry was looking like a potential performance win. /Jonas
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