hi,
I have faced the same question before.
The rf should be initialized before RTL simulation, otherwise, x value will
appear.
Actually, the initial of the registers can be done by firmware, probably
written in ASM.
However, if this is done by firmware, the initialization will take some cycles
when RTL simulation.
I have tried another way to do the initialization that is using a initial block
in testbech or testcase. At this circumstance, on more cycles are needed in RTL
simulation.
However, I have built a FPGA project, and download OR in FPGA, and found out
that the CPU runs well when there is no initialization of rf by firmware. Maybe
the default value of FPGA register is OK for CPU running.
Good Luck!
lobachevsky
From: Stefan Kristiansson
Date: 2011-12-16 05:53
To: Matthew Hicks
CC: openrisc; openrisc
Subject: Re: [OpenRISC] [OR1200][PATCH] Ignore writes to register 0
On 12/15/2011 11:15 PM, Matthew Hicks wrote:
> The current or1200 implementation allows any value to be written to r0, which
> is supposed to always be 0. The following patch basically ignores all writes
> to r0.
>
> Index: or1200_rf.v
> ===================================================================
> --- or1200_rf.v(revision 672)
> +++ or1200_rf.v(working copy)
> @@ -186,7 +186,7 @@
> //
> // RF write data is either from SPRS or normal from CPU datapath
> //
> -assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;
> + assign rf_dataw = (rf_addrw == 0) ? 32'b0 : (spr_valid & spr_write) ?
> spr_dat_i : dataw;
> //
> // RF write enable is either from SPRS or normal from CPU control
>
>
Although I don't see anything wrong with doing what you are proposing,
allowing writes to r0 is actually not a bug.
The arch manual states:
"R0 is used as a constant zero. Whether or not R0 is actually hardwired to zero
is
implementation dependent. R0 should never be used as a destination register."
Stefan
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