On Sat, 2012-04-21 at 16:18 +0100, Julius Baxter wrote: > On Sat, Apr 21, 2012 at 4:03 PM, Matthew Hicks <[email protected]> wrote: > > > > Agreed as it impacts other stuff least. I also think that CBFRI > > should be required as well. > > Hmmm, I was going to say that the functionality of the invalidate > block ensures that dirty data is written back (flushed) before > invalidating, but I've just checked and it says in 9.2.3: > > Modified data cache block is invalidated in all processors. > > So invalidate doesn't flush it :-S (kinda obvious from the name, though!) >
Invalidate is primarily interesting when somebody other than the processor has written to memory (DMA) and you want to be sure that CPU actually accesses the data in memory and not some stale value in cache. It would be fatal if invalidate implied a write-back as that would potentially be destroying the data that's there... > In this case, I'd say data cache block flush is mandatory too. I'd say these functions _could_ be optional, for a very limited use case. On a uniprocessor system without any devices doing DMA, your cache will always be coherent; other than at reset, you'd never need to invalidate the cache and you'd never need to flush it at all. So if there are any savings to be had by skipping those registers, this is where it is. The question is: what are the savings? Is it worth it? /Jonas _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
