2012/1/9 Stefan Kristiansson <[email protected]>: > On Sun, Jan 08, 2012 at 05:06:08PM +0100, Franck JULLIEN wrote: >> Hi, >> >> After make my CPU work under Modelsim, I started to take a look at the >> JTAG / debug interface when I realized I needed two JTAG on my board. >> >> As I'm using an Altera eval board (DE1 and NEEK), I have an integrated >> JTAG interface (hardware built-in into the board). >> So I need to use my USB-Blaster plugged on GPIOs using a special cable >> in order to get OpenOCD running. >> Doesn't sound's good and I don't like it. >> > > The DE boards in my orpsocv2 tree > (http://git.openrisc.net/cgit.cgi/stefan/orpsoc/tree/boards/altera) > has support for using the advanced debug system as an option > (http://opencores.org/project,adv_debug_sys) > That allows you to use the integrated JTAG interface to debug the CPU. > It's working, but I've hade som stability issues with it in my setup > and there is currently no support in OpenOCD for it (you'll need to use > proxy provided with adv_debug_sys). >
You're right the virtual JTAG is another option. However, it is Altera specific. I'll give it a try. >> I'm thinking of doing some UART to WISHBONE bus IP. This IP would have >> some GPIO (to control cpu reset for example) and a mechanism switching >> between the standard UART and the controlling software. The >> controlling software would be able to download files to RAM (or SPI >> FLASH, CFI,....), read/write/modify some addresses. >> > > Wouldn't that pretty much be achieved with a preloaded u-boot/barebox > and just a normal UART? Preloaded in internal RAM/ROM ? Barebox is about 100KB. But once it works you're right.... > >> This kind of interface would be slow but I think I worth it. It could >> be an easy way to run test program. >> >> I know there is already a comparable IP on Opencores. However, it is >> not wishbone compliant and I don't like to reuses someone else's code >> when it's not as a blackbox. >> Moreover, there is no controlling software. >> >> What do you think about this ? >> > > I'd like to direct valuable developer resources onto getting > advanced debug system support into OpenOCD ;) > I've been (half arsed) experimenting with using the altera vjtag together > with the old debug if (aka mohor) too with some minor success, > that's something that might be worth looking into too. > But in the end I think we want support for adv_debug_sys anyway. > > Stefan I'll take a look at your design and make some tests. Franck. _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
