Hi, After make my CPU work under Modelsim, I started to take a look at the JTAG / debug interface when I realized I needed two JTAG on my board.
As I'm using an Altera eval board (DE1 and NEEK), I have an integrated JTAG interface (hardware built-in into the board). So I need to use my USB-Blaster plugged on GPIOs using a special cable in order to get OpenOCD running. Doesn't sound's good and I don't like it. I'm thinking of doing some UART to WISHBONE bus IP. This IP would have some GPIO (to control cpu reset for example) and a mechanism switching between the standard UART and the controlling software. The controlling software would be able to download files to RAM (or SPI FLASH, CFI,....), read/write/modify some addresses. This kind of interface would be slow but I think I worth it. It could be an easy way to run test program. I know there is already a comparable IP on Opencores. However, it is not wishbone compliant and I don't like to reuses someone else's code when it's not as a blackbox. Moreover, there is no controlling software. What do you think about this ? Franck. _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
