Hi Julius:
> [...]
This is a good exercise, thanks for having a go. I recall I did a bit
of linting a while back and got through the CPU and Mohor debug IF.
Note that I believe there's still a couple of Verilator lint-off
directive comments in the code here and there.
> [...]
In order to get started, could you take a look at my first suggestion?
Here it is again:
--------8<--------8<--------
For example, I'm getting this warning for the OpenRISC core
included in ORPSoC2:
%Warning-DECLFILENAME: rtl/verilog/or1200/or1200_fpu_intfloat_conv.v:323:
Filename 'or1200_fpu_intfloat_conv' does not match MODULE name:
or1200_fpu_intfloat_conv_except
Could you move module 'or1200_fpu_intfloat_conv_except' to a new file
called 'or1200_fpu_intfloat_conv_except'? I've tried that locally and it
works. Alternatively, that module could be defined as a submodule of the
main one, but that's only available for SystemVerilog (2005). Do we need
to support older Verilog standards?
--------8<--------8<--------
Thanks in advance,
Ruben
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