> I'd say these functions _could_ be optional, for a very limited use > case. On a uniprocessor system without any devices doing DMA, your > cache will always be coherent; other than at reset, you'd never need to > invalidate the cache and you'd never need to flush it at all. So if > there are any savings to be had by skipping those registers, this is > where it is.
Just as a reminder, any wishbone masters connected to the ORPSoC / MinSoc arbiter other than the CPU core are actually DMA users, so they are more common than usually expected. For example, the Ethernet controller uses DMA exclusively in order to transfer data. The debugging support also uses DMA in order to read the memory contents while the CPU is stalled, and I think you can also write to memory from gdb when halted at a breakpoint, so the debugger should be able to invalidate the cache too. Therefore, if you have a cache, I'm guessing that you almost always need the ability to invalidate it. Regards, rdiez _______________________________________________ OpenRISC mailing list OpenRISC@lists.openrisc.net http://lists.openrisc.net/listinfo/openrisc
