On Sun, 2012-04-22 at 09:18 +0100, R. Diez wrote: > > > > I'd say these functions _could_ be optional, for a very limited use > > case. On a uniprocessor system without any devices doing DMA, your > > cache will always be coherent; other than at reset, you'd never need to > > invalidate the cache and you'd never need to flush it at all. So if > > there are any savings to be had by skipping those registers, this is > > where it is. > > Just as a reminder, any wishbone masters connected to the ORPSoC / MinSoc > arbiter other than the CPU core are actually DMA users, so they are more > common than usually expected. For example, the Ethernet controller uses DMA > exclusively in order to transfer data. > > The debugging support also uses DMA in order to read the memory contents > while the CPU is stalled, and I think you can also write to memory from gdb > when halted at a breakpoint, so the debugger should be able to invalidate the > cache too. > > Therefore, if you have a cache, I'm guessing that you almost always need the > ability to invalidate it.
What you write above is correct, but my point is still valid: if you _don't_ have any DMA devices, you don't need the cache write-back/invalidate operations during normal operation. For example, say you just have CPU core and a PIO I2C controller, without debug unit. Now you're in the clear and can live without those regs. That said, I don't personally have any use for such a configuration, so I'm not going to complain if this option is axed... but it _is_ a valid configuration that we have in a published specification today; it requires some thought before it's changed. /Jonas _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
