Hallo Pete: > So I just pushed to my repos on github a bunch of changes for both the > CGEN simulator and making the delay slot optional.
I'm trying to run my modified test suite against your simulator, and I'm getting the following warning when the test code accesses the SPR_EPCR_BASE register: WARNING: l.mfspr with invalid SPR address 0x20 Does the simulator support the OpenRISC exceptions and special registers? Thanks, rdiez _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
