On Tue, May 15, 2012 at 10:42 PM, R. Diez <[email protected]> wrote: > Hallo Pete: > >> So I just pushed to my repos on github a bunch of changes for both the >> CGEN simulator and making the delay slot optional. > > I'm trying to run my modified test suite against your simulator, and I'm > getting the following warning when the test code accesses the SPR_EPCR_BASE > register: > > WARNING: l.mfspr with invalid SPR address 0x20 > > Does the simulator support the OpenRISC exceptions and special registers?
Not really, not yet :) I didn't need them for the GCC testsuite. Right now the l.sys and l.trap instructions just call abort, I'm pretty sure. The l.mtspr/l.mfspr instructions are implemented, but I didn't implement many of the different SPR numbers. And that warning was so I could see if the GCC testsuite tried using an SPR I hadn't implemented yet. It shouldn't be hard to add that stuff, but if your testsuite tests virtual memory or the hardware devices, those tests won't pass. Virtual memory isn't really doable with this simulator, and probably won't ever be. -Pete _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
