> [...]
> functionality in it, but things like timers and interrupts aren't > there, and aren't really needed to test the code in the GCC testsuite. > > I agree that it looks like you won't get something like the MMU going. > [...] I was hoping to get support for at least the basic exceptions like "invalid instruction" or "range error", so that most of the simple test cases from other test suites (like division by zero) can run without modifications on the CGEN simulator. In my opinion, having a simulator designed to run a particular set of test cases is not such a good idea, as the simulator will tend to mask errors by adjusting itself to the test suite it's designed to run, instead of remaining true to the original arquitecture document. In fact, I had a quick go and I think the CGEN simulator fails some simple division tests (I have to check again). I wonder what other things are broken. > It's important to remember that the point of this sim is to run the > GCC testsuite and that's about all. This is very handy because it > removes the dependence on or1ksim when building the tool chain > (previously we had to build or1ksim before we built gdb.) Do you mean the simulator is only needed to run the GCC and/or GDB test suites? The whole point is then just to avoid having to build or1ksim beforehand? If that's the case, I don't think maintaining another (very crippled) simulator is worth the effort. As you know, I have written an automated build framework which can build and test everything together with little effort. The right thing to do would be to let the framework run all those checks against both or1ksim and an Icarus Verilog simulation of ORPSoC's or1200 core. Regards, rdiez _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
