On Fri, Sep 28, 2012 at 04:59:06PM -0400, Peter Gavin wrote: > On Fri, Sep 28, 2012 at 4:57 PM, Matthew Hicks <[email protected]> wrote: > > For a non-pipelined multiplier, using the Verilog multiply operator > > will produce the best results across a variety of FPGAs. > > But in order to detect overflow properly you'll have to do the > multiplication to the full 64 bits. >
Yes, but verilog '*' does that, no? What you also have to do to detect overflow properly is either produce seperate multipliers for signed and unsigned or convert the signed to unsigned before the multiplication and then convert back. The truncated result from a signed and unsigned multiply is the same. Stefan _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
