On Fri, Sep 28, 2012 at 10:43 PM, Stefan Kristiansson <[email protected]> wrote: > On Fri, Sep 28, 2012 at 04:59:06PM -0400, Peter Gavin wrote: >> On Fri, Sep 28, 2012 at 4:57 PM, Matthew Hicks <[email protected]> wrote: >> > For a non-pipelined multiplier, using the Verilog multiply operator >> > will produce the best results across a variety of FPGAs. >> >> But in order to detect overflow properly you'll have to do the >> multiplication to the full 64 bits. >> > > Yes, but verilog '*' does that, no? > > What you also have to do to detect overflow properly is either > produce seperate multipliers for signed and unsigned or > convert the signed to unsigned before the multiplication and then convert > back. > The truncated result from a signed and unsigned multiply is the same.
Yeah, and that's pretty straightforward and simple to implement the flags that way. I guess my gripe is just that the simplest implementation uses a full 32x32 to 64-bit multiply, but the ISA just throws away the top half. A better ISA would let you access that top half. You can't get to it, even if you use the MAC. -Pete _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
