On Fri, Sep 28, 2012 at 09:11:19PM +0200, R. Diez wrote: > Hi all OpenRISC gurus: > > I'd like to implement the multiply and divide ORBIS instructions on > my OR10 CPU. > > I did a quick research, and this area is not straightforward, or > maybe I haven't found the right website yet. I could invest more > time and study the existing implementations, but I'm hoping somebody > here can help me save a lot of time and effort. > > I guess implementing a generic multiplicator in pure Verilog will > end up taking a lot or resources, so I looked at the Xilinx > primitives / IP generator. The first thing I noticed is that there > are no carry or overflow signals. As discussed in this list before, > the existing or1200 implementation does not generate the same carry > and overflow results as or1ksim. Can anybody point me to a good > website where I can copy a correct Verilog carry/overflow > implementation from? Can I still use the Xilinx primitives to save > FGPA area and calculate carry/overflow separately? > > Should I go for a pipelined version, in order to let the rest of the > CPU run at a higher speed when not multiplying? I think or1200 has a > configuration option to disable carry and overflow, should I go > ahead with Xilinx's IP cores and leave carry and overflow out? Or > does GCC need them? > > Can I reuse a multiplicator somehow for signed and unsigned > integers, or do I have to implement one for each kind? > > Is there a Xilinx IP core to divide integers, or can I resort to > some other trick with other components? Or do I have to resort to a > pure Verilog implementation? >
For the division, I'd suggest you use a simple serial divider. Feel free to take inspiration from the one I did in mor1kx: https://github.com/openrisc/mor1kx/blob/master/rtl/verilog/mor1kx_execute_alu.v#L310 Stefan _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
