On Wed, Oct 17, 2012 at 4:55 PM, R. Diez <[email protected]> wrote: > Hi all: > > While testing my OR10 CPU with Verilator, I realised that the Wishbone bus > hangs when the CPU tries to access an invalid address like 0xF0000000. > > I took a quick look at the "Xess Traffic Cop" Wishbone switch used by MinSoC > and ORPSoC, which I'm using too, and the problem is probably that there is > no device (RAM or peripheral) that handles the address range starting with > F0. > > It does not seem like this Wishbone switch generates a bus error itself when > a master tries to access an address not covered by any of the attached > slaves.
The ones I wrote for ORPSoC (OK, not usefully parameterisable) do detect errors after a selectable time out, Olof said something about a nice one he'd written recently for ORPSoCv3 which was properly parametersiable. This perhaps: http://git.opencores.org/?a=viewblob&p=orpsoc&h=c108edbf1f67ea29f908d675dd44ee21ad5e9870&hb=97c96038a3ed68b6ad700e44e301afccf8d6033c&f=cores/wb_utils/wb_mux.v > > I would like to add some error-detection logic for this case. If saving FPGA > resources is more important than detecting invalid addresses, such a check > could be made optional. > > The trouble is, I don't understand how the Wishbone switch works. > Is anybody familiar enough with the implementation? Exactly which one are you using? Cheers Julius _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
