2012/10/17 Julius Baxter <[email protected]>: > On Wed, Oct 17, 2012 at 4:55 PM, R. Diez <[email protected]> wrote: >> Hi all: >> >> While testing my OR10 CPU with Verilator, I realised that the Wishbone bus >> hangs when the CPU tries to access an invalid address like 0xF0000000. >> >> I took a quick look at the "Xess Traffic Cop" Wishbone switch used by MinSoC >> and ORPSoC, which I'm using too, and the problem is probably that there is >> no device (RAM or peripheral) that handles the address range starting with >> F0. >> >> It does not seem like this Wishbone switch generates a bus error itself when >> a master tries to access an address not covered by any of the attached >> slaves. > > The ones I wrote for ORPSoC (OK, not usefully parameterisable) do > detect errors after a selectable time out, Olof said something about a > nice one he'd written recently for ORPSoCv3 which was properly > parametersiable. This perhaps: > http://git.opencores.org/?a=viewblob&p=orpsoc&h=c108edbf1f67ea29f908d675dd44ee21ad5e9870&hb=97c96038a3ed68b6ad700e44e301afccf8d6033c&f=cores/wb_utils/wb_mux.v >
Yes, I'm working on this right now. That links to the mux part (1 master, multiple slaves). I still need to do some verification on the arbiter part (multiple masters, one slave) before I check it in. The watchdog stuff is stolen from Julius' orpsocv2 implementation, so that should reply with an error after a timeout for invalid addresses -- Olof Kindgren ______________________________________________ ORSoC Website: www.orsoc.se Email: [email protected] ______________________________________________ FPGA, ASIC, DSP - embedded SoC design _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
