On Mon, Jul 15, 2013 at 11:01 PM, Luís Vitório Cargnini <[email protected]> wrote: > Hello, > > recently I've been synthesizing the OpenRISC for 28nm SAED32 and looking > into the schematic I noticed it has only 1-way cache. > > How can I change it to 4-way associative ?
Hi, Which core? There are several synthesisable OR1K-compliant CPUs. http://opencores.org/or1k/OR1K_CPU_Cores I'll guess you're talking about the OR1200 here. I don't think think the OR1200 has more than a direct mapped (1-way) cache but the mor1kx has either direct mapped or 2-way. Cheers Julius _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
